ClaytonWWilson/miryoku_zmk
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Add combos of primary and secondary thumbs to emulate tertiary thumb

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This commit is contained in:
Manna Harbour 2021-02-23 16:31:13 +11:00
parent a469ad4b46
commit 73b4484f63
6 changed files with 210 additions and 51 deletions
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3
config/corne.keymap
View File

@ -1,3 +1,6 @@
#include "../miryoku/split_3x6_3.h" #include "../miryoku/split_3x6_3.h"
#define MIRYOKU_COMBO_TPS_ENABLE
#include "../miryoku/miryoku.dtsi" #include "../miryoku/miryoku.dtsi"

80
miryoku/miryoku-zmk.org
View File

@ -911,6 +911,10 @@ layout is mapped onto keyboards with different physical layouts as a subset.
*** [[split_3x5_2.h]] *** [[split_3x5_2.h]]
Combos of primary and secondary thumb keys emulate the missing tertiary thumb
key. To enable with other subset mappings for compatibility, add ~#define
MIRYOKU_COMBO_TPS_ENABLE~ to the keymap before the includes.
#+BEGIN_SRC C :noweb yes :padline no :tangle split_3x5_2.h #+BEGIN_SRC C :noweb yes :padline no :tangle split_3x5_2.h
// <<header>> // <<header>>
@ -928,6 +932,11 @@ K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 \
K33 K34 K35 K36 K33 K34 K35 K36
#define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP #define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP
#define MIRYOKU_COMBO_TPSL 30 31
#define MIRYOKU_COMBO_TPSR 32 33
#define MIRYOKU_COMBO_TPS_ENABLE
#+END_SRC #+END_SRC
@ -950,6 +959,9 @@ K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 \
K32 K33 K34 K35 K36 K37 K32 K33 K34 K35 K36 K37
#define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP #define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP
#define MIRYOKU_COMBO_TPSL 33 34
#define MIRYOKU_COMBO_TPSR 35 36
#+END_SRC #+END_SRC
@ -981,6 +993,9 @@ XXX K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 XXX \
&kp LCTRL K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 &kp RCTRL \ &kp LCTRL K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 &kp RCTRL \
&kp LSHFT K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 &kp RSHFT \ &kp LSHFT K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 &kp RSHFT \
K32 K33 K34 K35 K36 K37 K32 K33 K34 K35 K36 K37
#define MIRYOKU_COMBO_TPSL 37 38
#define MIRYOKU_COMBO_TPSR 39 40
#+END_SRC #+END_SRC
@ -1057,6 +1072,9 @@ K20 K21 K22 K23 K24 &kp NUM_4 &kp NUM_3 K25 K26 K27 K28 K
bindings = <&kp>, <&kp>; bindings = <&kp>, <&kp>;
}; };
}; };
};
/ {
keymap { keymap {
compatible = "zmk,keymap"; compatible = "zmk,keymap";
BASE_layer { BASE_layer {
@ -1194,6 +1212,68 @@ K20 K21 K22 K23 K24 &kp NUM_4 &kp NUM_3 K25 K26 K27 K28 K
}; };
}; };
}; };
#if defined (MIRYOKU_COMBO_TPS_ENABLE) && defined (MIRYOKU_COMBO_TPSL) && defined (MIRYOKU_COMBO_TPSR)
/ {
combos {
compatible = "zmk,combos";
combo_tpsl_BASE {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&lt MEDR ESC>;
layers = <BASE>;
};
combo_tpsr_BASE {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <&lt FUNL DEL>;
layers = <BASE>;
};
combo_tpsr_MBO {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <U_NU>;
layers = <MBO>;
};
combo_tpsr_NAVR {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <&kp DEL>;
layers = <NAVR>;
};
combo_tpsr_MOUR {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <U_NU>;
layers = <MOUR>;
};
combo_tpsr_MEDR {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <&kp K_MUTE>;
layers = <MEDR>;
};
combo_tpsl_NSL {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&kp DOT>;
layers = <NSL>;
};
combo_tpsl_NSSL {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&kp LPAR>;
layers = <NSSL>;
};
combo_tpsl_FUNL {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&kp K_APP>;
layers = <FUNL>;
};
};
};
#endif
#+END_SRC #+END_SRC

65
miryoku/miryoku.dtsi
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@ -58,6 +58,9 @@
bindings = <&kp>, <&kp>; bindings = <&kp>, <&kp>;
}; };
}; };
};
/ {
keymap { keymap {
compatible = "zmk,keymap"; compatible = "zmk,keymap";
BASE_layer { BASE_layer {
@ -267,3 +270,65 @@ U_NP, U_NP, &kp K_APP, &kp SPC, &kp TAB, U_NA, U_
}; };
}; };
}; };
#if defined (MIRYOKU_COMBO_TPS_ENABLE) && defined (MIRYOKU_COMBO_TPSL) && defined (MIRYOKU_COMBO_TPSR)
/ {
combos {
compatible = "zmk,combos";
combo_tpsl_BASE {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&lt MEDR ESC>;
layers = <BASE>;
};
combo_tpsr_BASE {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <&lt FUNL DEL>;
layers = <BASE>;
};
combo_tpsr_MBO {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <U_NU>;
layers = <MBO>;
};
combo_tpsr_NAVR {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <&kp DEL>;
layers = <NAVR>;
};
combo_tpsr_MOUR {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <U_NU>;
layers = <MOUR>;
};
combo_tpsr_MEDR {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSR>;
bindings = <&kp K_MUTE>;
layers = <MEDR>;
};
combo_tpsl_NSL {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&kp DOT>;
layers = <NSL>;
};
combo_tpsl_NSSL {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&kp LPAR>;
layers = <NSSL>;
};
combo_tpsl_FUNL {
timeout-ms = <200>;
key-positions = <MIRYOKU_COMBO_TPSL>;
bindings = <&kp K_APP>;
layers = <FUNL>;
};
};
};
#endif

5
miryoku/split_3x5_2.h
View File

@ -14,3 +14,8 @@ K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 \
K33 K34 K35 K36 K33 K34 K35 K36
#define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP #define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP
#define MIRYOKU_COMBO_TPSL 30 31
#define MIRYOKU_COMBO_TPSR 32 33
#define MIRYOKU_COMBO_TPS_ENABLE

3
miryoku/split_3x5_3.h
View File

@ -14,3 +14,6 @@ K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 \
K32 K33 K34 K35 K36 K37 K32 K33 K34 K35 K36 K37
#define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP #define MIRYOKU_SUPERMAP MIRYOKU_SUBMAP
#define MIRYOKU_COMBO_TPSL 33 34
#define MIRYOKU_COMBO_TPSR 35 36

3
miryoku/split_3x6_3.h
View File

@ -23,3 +23,6 @@ XXX K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 XXX \
&kp LCTRL K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 &kp RCTRL \ &kp LCTRL K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 &kp RCTRL \
&kp LSHFT K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 &kp RSHFT \ &kp LSHFT K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 &kp RSHFT \
K32 K33 K34 K35 K36 K37 K32 K33 K34 K35 K36 K37
#define MIRYOKU_COMBO_TPSL 37 38
#define MIRYOKU_COMBO_TPSR 39 40